Location: Pasadena, CA 91109

Full/Part-time: Full Time

Pay Range: $64.15-$98.60/hour

Duration: 23 months or longer

Work schedule: 9/80 – 1st shift- Telework eligible 2 days per week

Citizenship: Permanent Resident or US Citizen

Travel: None

Summary:

SSAI seeks a FPGA Design Engineer to support work at Jet Propulsion Laboratory, (JPL) National Aeronautics and Space Administration, (NASA) in Pasadena, CA. As a principal level FPGA Design Engineer, you will lead the planning and execution of highly sophisticated and unique electronics systems with Laboratory wide impact. Specific responsibilities include:

• Lead, design, and deliver a verified fight qualified FPGA
• Improve FPGA design flow
• Improve hardware resilience techniques
• Apply digital design knowledge and principles to extremely complex designs
• Mentor junior engineers

Required Qualifications:

• Bachelor’s degree in Electronics, Electrical, or Computer Engineering or related discipline with typically a minimum of 9 years of related experience; Master’s in similar disciplines with a minimum of 7 years of related experience; or PhD in similar disciplines with a minimum of 5 years of related experience
• Expert in architecting, designing, implementing, and testing advanced digital systems
• Fluent coding in Verilog and System Verilog
• Extensive experience crafting FPGAs and embedded processors designs using tools: Synplify Pro/Premier, Xilinx Vivado, Microsemi Libero SoC, and Mentor Graphics Questa design suite
• Demonstrated experience leading team and presenting in design reviews
• Must be successful leading FPGA/ASIC designs through full life cycle from initial concept to burn review.
• Success infusing new design/verification technologies and methodologies
• Skillfully handles fast pace and dynamic product development environment
• Outstanding leader able to build consensus as well as excellent written/verbal communication skills

Desired Qualifications:

• Experience designing with radiation tolerant Xilinx and Microsemi FPGAs
• Experience in bus standards protocol such as: SpaceWire, PCI, MILSTD-1553, CAN, and Ethernet
• Embedded Software knowledge and experience
• SystemC or C++, Matlab
• Experience with digital twin modeling
• Familiar with Failure Analysis and worst-case analysis

About our client:

Our client is a research and development lab federally funded by NASA and managed by Caltech. JPL manages many of NASA's robotic missions exploring Earth, the solar system, and our universe.

This client is requiring that all new hires show proof of vaccination. However, accommodations may be made for those with medical or religious reasons and are unable to obtain a vaccine.

About SSAI:

As a leading provider of support services for more than 45 years, our expert professionals share a commitment to providing solutions for the unique needs of each client.

Benefits: We offer paid time off, holidays, 401k, medical, dental, and vision.

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  At a minimum, a 7-year background check, education verification, employment verification, and drug screen will be conducted upon hire. Your suitability for employment is contingent upon successfully passing these required pre-employment screenings.

Don't miss out on this amazing opportunity! If you feel your experience is the match for this position, please apply today and join our team. We look forward to working with you!

EEO- including disability/vets